add cortex-m0 support to aapcs_elf_gas target.

some instruction used here is not available on Cortex-M0, aka, subjective to Cortex-M4.
I'm using boost_fcontext on some M0 based MCU for cooperative multi tasking.
Adding this ifdef guard make sure these code runs fun on Cortex-M0 based MCU.

src/asm/jump_arm_aapcs_elf_gas.S

@@ -49,8 +49,38 @@ jump_fcontext:
     @ save LR as PC
     push {lr}
     @ save hidden,V1-V8,LR
+
+    #if __ARM_ARCH >= 7
+
     push {a1,v1-v8,lr}
 
+    #else
+
+    sub  sp, #40
+
+    str a1, [sp, #0]
+    str v1, [sp, #4]
+    str v2, [sp, #8]
+    str v3, [sp, #12]
+    str v4, [sp, #16]
+
+    mov v4, v5
+    str v4, [sp, #20]
+
+    mov v4, v6
+    str v4, [sp, #24]
+
+    mov v4, v7
+    str v4, [sp, #28]
+
+    mov v4, v8
+    str v4, [sp, #32]
+
+    mov v4, lr
+    str v4, [sp, #36]
+
+    #endif
+
     @ prepare stack for FPU
     sub  sp, sp, #64
 #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
@@ -72,7 +102,34 @@ jump_fcontext:
     add  sp, sp, #64
 
     @ restore hidden,V1-V8,LR
+    #if __ARM_ARCH >= 7
     pop {a4,v1-v8,lr}
+    #else
+
+    ldr v4, [sp, #20]
+    mov v5, v4
+
+    ldr v4, [sp, #24]
+    mov v6, v4
+
+    ldr v4, [sp, #28]
+    mov v7, v4
+
+    ldr v4, [sp, #32]
+    mov v8, v4
+
+    ldr v4, [sp, #36]
+    mov lr, v4
+
+    ldr a4, [sp, #0]
+    ldr v1, [sp, #4]
+    ldr v2, [sp, #8]
+    ldr v3, [sp, #12]
+    ldr v4, [sp, #16]
+
+    add sp, #40
+
+    #endif
 
     @ return transfer_t from jump
     str  a1, [a4, #0]

src/asm/make_arm_aapcs_elf_gas.S

@@ -47,21 +47,41 @@
 .syntax unified
 make_fcontext:
     @ shift address in A1 to lower 16 byte boundary
+
+    #if __ARM_ARCH >= 7
     bic  a1, a1, #15
+    #else
+    lsrs	a1, a1, #4
+    lsls	a1, a1, #4
+    #endif
 
     @ reserve space for context-data on context-stack
+    #if __ARM_ARCH >= 7
     sub  a1, a1, #124
+    #else
+    subs  a1, #124
+    #endif
 
     @ third arg of make_fcontext() == address of context-function
     str  a3, [a1, #104]
 
     @ compute address of returned transfer_t
+    #if __ARM_ARCH >= 7
     add  a2, a1, #108
+    #else
+    mov  a2, a1
+    adds  a2, #108
+    #endif
     mov  a3, a2
     str  a3, [a1, #64]
 
+
     @ compute abs address of label finish
+    #if __ARM_ARCH >= 7
     adr  a2, finish
+    #else
+    ldr  a2, =finish
+    #endif
     @ save address of finish as return-address for context-function
     @ will be entered after context-function returns
     str  a2, [a1, #100]
@@ -73,7 +93,13 @@ make_fcontext:
 
 finish:
     @ exit code is zero
+    #if __ARM_ARCH >=7
     mov  a1, #0
+    #else
+    movs	r3, #0
+    movs	r0, r3
+    #endif
+
     @ exit application
     bl  _exit@PLT
 .size make_fcontext,.-make_fcontext

src/asm/ontop_arm_aapcs_elf_gas.S

@@ -49,8 +49,37 @@ ontop_fcontext:
     @ save LR as PC
     push {lr}
     @ save hidden,V1-V8,LR
+    #if __ARM_ARCH >= 7
+
     push {a1,v1-v8,lr}
 
+    #else
+
+    sub  sp, #40
+
+    str a1, [sp, #0]
+    str v1, [sp, #4]
+    str v2, [sp, #8]
+    str v3, [sp, #12]
+    str v4, [sp, #16]
+
+    mov v4, v5
+    str v4, [sp, #20]
+
+    mov v4, v6
+    str v4, [sp, #24]
+
+    mov v4, v7
+    str v4, [sp, #28]
+
+    mov v4, v8
+    str v4, [sp, #32]
+
+    mov v4, lr
+    str v4, [sp, #36]
+
+    #endif
+
     @ prepare stack for FPU
     sub  sp, sp, #64
 #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
@@ -75,7 +104,34 @@ ontop_fcontext:
     add  sp, sp, #64
 
     @ restore hidden,V1-V8,LR
+    #if __ARM_ARCH >= 7
     pop {a1,v1-v8,lr}
+    #else
+
+    ldr v4, [sp, #20]
+    mov v5, v4
+
+    ldr v4, [sp, #24]
+    mov v6, v4
+
+    ldr v4, [sp, #28]
+    mov v7, v4
+
+    ldr v4, [sp, #32]
+    mov v8, v4
+
+    ldr v4, [sp, #36]
+    mov lr, v4
+
+    ldr a1, [sp, #0]
+    ldr v1, [sp, #4]
+    ldr v2, [sp, #8]
+    ldr v3, [sp, #12]
+    ldr v4, [sp, #16]
+
+    add sp, #40
+
+    #endif
 
     @ return transfer_t from jump
     str  a2, [a1, #0]